The present invention relates to a write compensator for a magnetic recording/reproducing apparatus for performing high-density recording.
In a magnetic disk apparatus for performing high-density recording, a peak shift occurs in a data pulse due to the influence of adjacent bits when data is read out from a disk. This decreases time margins for data and clock windows When the margins are excessively decreased, an error rate is increased.
FIGS. 1A through 1E show a case wherein recording data externally transferred in the nonreturn-to-zero (NRZ) format for high-density recording is converted into recording data in the modified frequency modulation (MFM) format, and the converted data is written in a recording medium. FIG. 1A shows a data transfer reference clock, and FIG. 1B shows NRZ recording data. The NRZ recording data shown in FIG. 1B is transferred in synchronism with the reference clock shown in FIG. 1A. The NRZ recording data is converted into MFM recording data shown in FIG. 1E in accordance with MFM conversion rules in the magnetic disk apparatus in response to clock and data pulses shown in FIGS. 1C and 1D. The converted data is written in the magnetic recording medium. In this case, peak shifts occur in the data patterns shown in FIGS. 2A through 2D.
As shown in FIGS. 3A through 3P, peak shift directions are changed in accordance with different data pulse trains, as indicated by arrows. For example, referring to FIG. 3B, clock pulse C2 repulses clock and data pulses C1 and D1. In this case, clock pulse C2 is closer to clock pulse C1 than to data pulse D1. Therefore, clock pulse C2 repulses clock pulse C1 and is shifted in a direction of the arrow. Referring to FIG. 3D, data pulse D2 is closer to data pulse D3 than to clock pulse C3. Therefore, data pulse D2 repulses data pulse D3 and is shifted in a direction of the arrow.
Peak shifts can be predicted in the data write mode in accordance with data pulse patterns. Data patterns subjected to peak shifts are summarized as follows. When data pulse patterns are "0001" and "110" as shown in FIG. 4, late peak shifts occur. However, if data pulse patterns are "011" and "1000", early peak shifts occur, as shown in FIG. 4. Therefore, when recording data have patterns "011" and "1000", respectively, the data are shifted in directions of the arrows (right direction) in FIGS. 2A and 2B, i.e., in directions opposite to the read direction. However, when recording data have patterns "110" and "0001", repectively, data are shifted in directions of the arrows (left direction) in FIGS. 2C and 2D, thereby achieving write compensation.
Write compensation is conventionally performed by a write compensator shown in FIG. 5. Shift register 11 stores externally transferred NRZ recording data S1 in synchronism with reference clock signal CS1 and outputs it to decoder 13.
Decoder 13 has a function for converting NRZ recording data S1 into MFM recording data S2 and a function for producing write compensation information by decoding a pattern of data S2. More specifically, NRZ recording data S1 is converted into MFM recording data S2 in response to reference clock signals CS1 and CS2. The pattern of data S2 is decoded to generate signal S13a for compensation in an "early direction (i.e., a direction in which a write timing advances), noncompensation signal 13b, or signal 13c for compensation in a "late" direction (i.e., a direction in which a write timing is delayed). Signal 13a, 13b, or 13c is output to NAND gate 15.
Delay circuit 17 delays reference clock signal CS2 by delay times D0, D1, and D2 to obtain signals S17a, S17b, and S17c. Signals S17a, S17b, and S17c are input to NAND gate 15. logically NANDed by NAND gate 15 with signals S17a, S17b, and S17c from delay circuit 17. Output signals S15a, S15b, and S15c from NAND gate 15 are input to NAND gate 19. Signals S15a, S15b, and S15c are logically NANDed by NAND gate 19, and NAND gate 19 outputs writecompensated MFM recording data S19.
The operation of the write compensator having the arrangement described above will be described with reference to timing charts of FIGS. 6A through 6G. Externally transferred NRZ recording data S1 (FIG. 6C) is input to shift register 11 at the trailing edge of reference clock signal CS1 (FIG. 6B). In this case, shift register 11 comprises a 4-bit shift register. Recording data S1 is shifted in response to every clock CS1.
When recording data S1 is stored in shift register 11, data S1 is output to decoder 13. Decoder 13 decodes recording data S1 (FIG. 6C) from register 11 in response to reference clock signals CS1 and CS2 and generates MFM recording data S2 (FIG. 6D). Two reference clock signals CS1 and CS2 are used to assure accurate synchronization timings. In this case, a sync signal required in write compensation is signal CS1, and signal CS1 must be a signal having an accurate waveform. For this reason, signal CS2 having a frequency twice that of signal CS1 is produced and is frequency-divided to generate signal CS1 having an accurate waveform.
Decoder 13 decodes the pattern of converted recording data S2 to determine necessity of write compensation and generates write compensation information as needed. Compensation information signal S13a (FIG. 6E) for compensating recording data S2 in the early direction, noncompensation information signal S13b and compensation information signal S13c (FIG. 6F) for compensating data S2 in the late direction are output from decoder 13 to NAND gate 15. Since the pattern of recording data S1 is "0001", as shown in FIG. 6C, pulse 35 in recording data S2 is delayed, as shown in FIG. 6D. Signal S13a for compensating the write timing in the early direction is output between trailing edges 31a and 31b of reference clock signal CS1. As shown in FIG. 6D, pulse 37 in recording data S2 is advanced. Therefore, signal S13c for compensating the write timing in the late direction is output between trailing edges 33a and 33b of reference clock signal CS1. Noncompensation information signal S3b (not shown) is output for pulses not subjected to compensation between the current and next trailing edges of reference clock signal CS1.
At the same time, delayed signals S17a, S17b, and S17c obtained by delaying reference clock signal CS2 by delay times D0, D1, and D2 are output from delay circuit 17 to NAND gate 15.
Signals S13a, S13b, and S13c from decoder 13 and signals S17a, S17b, and S17c from delay circuit 17 are logically NANDed by NAND gate 15, and output signals S15a, S15b, and S15c therefrom are output to NAND gate 19. Signals S15a, S15b, and S15c from NAND gate 15 are logically NANDed by NAND gate 19. Write-compensated MFM recording data S19 is output from NAND gate 19.
FIG. 6G shows write-compensated MFM recording data. No shift occurs in MFM recording data 41 in FIG. 6D. Delay time D1 is assigned to pulse 41 as indicated by pulse 43 in FIG. 6G. However, since pulse 35 in FIG. 6D is shifted in the late direction, delay time D0, which is shorter than delay time D1, is given to pulse 35 to compensate for the time (D1-D0) in the early direction (direction indicated by arrow 51), as indicated by pulse 45 in FIG. 6G. Pulse 37 is shifted in the early direction, as shown in FIG. 6D. Therefore, delay time D2, which is longer than delay time D1, is given to pulse 37 to compensate for the time (D2-D1) in the late direction (direction indicated by arrow 53), as indicated by pulse 47 in FIG. 6G.
In the conventional magnetic disk apparatus for performing high-density recording, the above write compensator is used to automatically shift write timings in a direction to reduce peak shifts
In the write compensator shown in FIG. 5, however, write compensation information is derived using a reference clock signal as a reference. Therefore, the delay time length of the write compensation information signal is determined by the duration of the reference clock signal. Time length J of signal S13a for compensating write timings in the early direction and time length K of signal S13c for compensating the write timings in the late direction, as shown in FIG. 6E, must fall within the length of time between the current and next trailing edges of reference clock signal CS1 due to the following reason. Recording data S1 is shifted and shift register 11 outputs different values to decoder 13 whenever reference signal CS1 is input to shift register 11. Decoder 13 must completely decode the input before the output signal from register 11 is updated. Therefore, each delay time length of signals S13a, S13b, and S13c cannot exceed one cycle of reference signal CS1. Therefore, ranges of delay times D0, D1, and D2 (i.e., delay times D0, D1, and D2 of signals S17a, S17b, and S17c) of write-compensated recording data S19 are solely determined.
When the circuit is designed in practice, operating times of shift register 11 and decoder 13 must be taken into consideration, and the lengths of delay times D0, D1 and D2 are further shortened. Therefore, delay times D0, D1, and D2 cannot be flexible The absence of flexibility poses a problem when the recording density is increased.